Optimal Low Power Deduction using Clock Gating

Abstract

The tremendous rise in demand for smartphones brings the need for power optimization. In this generation, as the technology node changes as generation progresses the urge to minimize power utilization increased. The study portrays the integration of additional sensor and control units over the silicon to source the dynamic power consumption. The reduction in the technology node of the CMOS technology has continued to rise due the ever increase in the demand for greater performance devices with lower power consumption. To accept the challenge, the desire to implement newer and more optimization techniques at processor and system level has come into limelight.